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March 2007
HYB18M 1G 320 B F- 7 . 5 HYE18M 1G 320 B F- 7 . 5
DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM RoHS compliant
Data S heet
Rev.1.00
Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
HYB18M1G320BF-7.5, HYE18M1G320BF-7.5, Revision History: 2007-03, Rev.1.00 Page All All Subjects (major changes since last revision) Portfolio Change Qimonda update Updates see Change List
Previous Revision: Rev. 0.61, 2007-02
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
1
1.1
* * * * * * * * * * * * * * * * *
Overview
Features
Low power DDR 1Gbit x32 dual die implementation Each die is organized as 4 banks x 8 Mbit x16 Double-data-rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver DQS is edge-aligned with data for READs and center-aligned with data for WRITEs Differential clock input (CK / CK) Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS Four internal banks for concurrent operation Programmable CAS latency: 2 and 3 Programmable burst length: 2, 4, 8 and 16 Programmable drive strength (full, half, quarter) Auto refresh and self refresh modes 8192 refresh cycles / 64ms Auto precharge Commercial (-0C to +70C) and Extended (-25C to +85C) operating temperature ranges 90-ball PG-VFBGA-90-5 package (11 x 12.5 x 1.0 mm) RoHS Compliant Product1)
Power Saving Features * * * * * * Low supply voltages: VDD and VDDQ = 1.80 V nominal Optimized operating (IDD0, IDD4), self refresh (IDD6) and standby currents (IDD2, IDD3) DDR I/O scheme with no DLL Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Clock Stop, Power-Down and Deep Power-Down modes
TABLE 1
Performance
Part Number Speed Code Clock Frequency (fCKmax) Access Time (tACmax) CL = 3 CL = 2 133 66 6.5 - 7.5 MHz MHz ns Unit
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 2
Memory Addressing Scheme
Item Banks Rows Columns Addresses BA0, BA1 A0 - A12 A0 - A9
TABLE 3
Ordering Information
Type1) HYB18M1G320BF-7.5 Extended Temperature Range HYE18M1G320BF-7.5 133 MHz 4 Banks x 8 Mbit x 32 Low Power DDR Mobile-RAM
1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range) 18M: 1.8V DDR Mobile-RAM 1G: 1Gbit density 320: 32 bit interface width B: die revision F: green product -7.5: speed grades (min. clock cycle time)
Description 133 MHz 4 Banks x 8 Mbit x 32 Low Power DDR Mobile-RAM
Commercial Temperature Range
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
1.2
Ball Configuration
FIGURE 1
Standard ballout 1-Gbit DDR Mobile-RAM (Top View)
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
1.3
Description
The HY[B/E]18M1G320BF is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18M1G320BF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O balls. The HY[B/E]18M1G320BF is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD) mode. For further power-savings the clock may be stopped during idle periods. The HY[B/E]18M1G320BF is housed in a 90-ball PG-VFBGA-90-5 package. It is available in Commercial (-0C to +70C) and Extended (-25C to +85C) temperature range.
FIGURE 2
Functional Block Diagram
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
1.4
Ball Definition and Description
TABLE 4
Ball Description
Ball CK, CK CKE Type Input Input Detailed Function Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus (32 bit) Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. DQS0 corresponds to the data on DQ0 - DQ7, DQS1 to the data on DQ8 - DQ15, DQS2 to the data on DQ16 - DQ23, DQS3 to the data on DQ24 - DQ31 Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input only, the DM loading matches the DQ and DQS loading. DM may be driven HIGH, LOW, or floating during READs. DM0 corresponds to the data on DQ0 DQ7, DM1 to the data on DQ8 - DQ15, DM2 to the data on DQ16 - DQ23, DM3 to the data on DQ24 - DQ31 Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity I/O Ground Power Supply: Power for the core logic and input buffers. Ground No Connect
CS RAS, CAS, WE DQ0 - DQ31
Input Input I/O
DQS0, DQS1, I/O DQS2, DQS3
DM0, DM1, DM2, DM3
Input
BA0, BA1
Input
A0 - A12
Input
VDDQ VSSQ VDD VSS
N.C.
Supply Supply Supply Supply -
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2
Functional Description
The 1-Gbit x32 DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The DDR Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational procedures other than those specified may result in undefined operation.
FIGURE 3
Power-Up Sequence and Mode Register Sets
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HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ are driven from a single power converter output. Assert and hold CKE to a HIGH level. 2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks. 3. Wait for 200s while issuing NOP or DESELECT commands. 4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period. 5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC period. 6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both registers are programmed is not important. Following these steps, the DDR Mobile-RAM is ready for normal operation.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.2
Register Definition
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Mode Register Definition (BA[1:0] = 00B)
Field CL
Bits [6:4]
Type w
Description CAS Latency 010B CL 2 011B CL 3 Note: All other bit combinations are RESERVED. Burst Type BT Sequential 0B 1B BT Interleaved Burst Length 001B BL 2 010B BL 4 011B BL 8 100B BL 16 Note: All other bit combinations are RESERVED.
BT
3
w
BL
[2:0]
w
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.2.1.1
Burst Length
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, 8 or 16 locations are available. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1 - A9 when the burst length is set to two, by A2 - A9 when the burst length is set to four, by A3 - A9 when the burst length is set to eight and by A4 - A9 when the burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5.
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks. If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 * tCK + tAC). If a READ command is registered and the latency is 2 clocks, the first data element will be valid after (tCK + tAC). For details please refer to the READ command description.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 5
Burst Definition
Burst Length Starting Column Address A3 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Notes 1. 2. 3. 4. 5. For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block. For a burst length of 16, A4-Ai select the sixteen-data-element block; A0-A3 select the first access within the block. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A2 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E Order of Accesses Within a Burst (Hexadecimal Notation) Sequential 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 Interleaved
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.2.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - A12 shall be written to zero. Bits A3 and A4 are "don't care" (see below). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Extended Mode Register Definition (BA[1:0] = 10B)
Field DS
Bits [6:5]
Type w
Description Selectable Drive Strength 00B DS Full Drive Strength 01B DS Half Drive Strength 10B DS Quarter Drive Strength Note: All other bit combinations are RESERVED. Temperature Compensated Self Refresh XXB TCSR Superseded by on-chip temperature sensor (see text) Partial Array Self Refresh 000B PASR all banks 001B PASR half array (BA1 = 0) 010B PASR quarter array (BA1 = BA0 = 0) 101B PASR 1/8 array (BA1 = BA0 = RA12 = 0) 110B PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0) Note: All other bit combinations are RESERVED.
TCSR
[4:3]
w w
PASR [2:0]
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.2.2.1
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by tREF (cf. Table 14).
2.2.2.2
Temperature Compensated Self Refresh (TCSR) with OnChip Temperature Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh periods, and low temperatures correspond to long refresh periods. The DDR Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because * it is fully compatible to all processors that do not support the Extended Mode Register * it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an external temperature sensor * it does not require any processor interaction for regular TCSR updates
2.2.2.3
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6. The "full drive strength" (default) is suitable for heavier loaded systems. The "half drive strength" is intended for lightly loaded systems or systems with reduced performance requirements. For systems with point-to-point connection, a "quarter drive strength" is available. I-V curves for full and half drive strengths are included in this document.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.3
State Diagram
FIGURE 4
State Diagram
Deep Power Down
Power applied
Power On
DPDSX
Precharge All Banks
DPDS REFSX
Self Refresh
Idle MRS EMRS
MRS
REFS REFA CKEL CKEH
All banks precharged
Auto Refresh
Active Power Down
CKEH CKEL
ACT
Precharge Power Down
Row Active
READ
Burst Stop
WRITE WRITE WRITEA
BST READA READ
READ
WRITE
READ
WRITEA
READA PRE PRE PRE
READA
WRITE A
READ A
PRE
Precharge PREALL Automatic Sequence Command Sequence
ACT = Active BST = Burst Terminate CKEL = Enter Power-Down CKEH = Exit Power-Down DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-Down
EMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = Precharge PREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self Refresh
REFSX = Exit Self Refresh READ = Read w/o Auto Precharge READA = Read with Auto Precharge WRITE = Write w/o Auto Precharge WRITEA = Write with Auto Precharge
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and commands to control them, not all details. In particular situations involving more than one bank are not captured in full detail.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4
Commands
TABLE 6
Command Overview
Command NOP ACT RD WR BST PRE ARF MRS
1) 2) 3) 4) 5)
CS H L L L L L L L L
RAS X H L H H H L L L
CAS X H H L L H H L L
WE X H H H L L L H L X X
Address
Note
1)2) 1)2) 1)3) 1)4) 1)4) 1)5) 1)6) 1)7)8) 1)9)
DESELECT NO OPERATION ACTIVE (Select bank and row) READ (Select bank and column and start read burst) WRITE (Select bank and column and start write burst) BURST TERMINATE or DEEP POWER-DOWN PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH entry MODE REGISTER SET
Bank / Row Bank / Col Bank / Col X Code X Op-Code
6) 7) 8) 9)
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN. DESELECT and NOP are functionally interchangeable. BA0, BA1 provide the bank address, and A0 - A12 provide the row address. BA0, BA1 provide the bank address, A0 - A9 provide the column address; A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature. This command is BURST TERMINATE if CKE is HIGH, DEEP POWER-DOWN if CKE is LOW. The BURST TERMINATE command is defined for READ bursts with Auto Precharge disabled only; it is undefined (and should not be used) for read bursts with Auto Precharge enabled, and for write bursts. A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
TABLE 7
DM Operation
Name (Function) Write Enable Write Inhibit
1) Used to mask write data provided coincident with the corresponding data
DM L H
DQs Valid X
Note
1) 1)
Address (BA0, BA1, A0 - A12) and command inputs (CKE, CS, RAS, CAS, WE) are all registered on the crossing of the positive edge of CK and the negative edge of CK. Figure 5 shows the basic timing parameters, which apply to all commands and operations.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 5
Address / Command Inputs Timing Parameters
tCK CK CK tIS tIH Valid Valid Valid = Don't Care tCH tCL
Input
TABLE 8
Inputs Timing Parameters
Parameter Symbol min. Clock high-level width Clock low-level width Clock cycle time Address and control input setup time Address and control input hold time Address and control input pulse width
1) 2) 3) 4) 5) 6) 7)
- 7.5 max. 0.55 0.55 - - - - - - -
Unit
Note
tCH tCL CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate tIPW tIH tIS tCK
0.45 0.45 7.5 15 1.3 1.5 1.3 1.5 3.0
tCK tCK ns ns ns ns
1) 1) 1)2)
1)3)4)5) 1)3)6) 1)3)4) 1)3)6) 1)7)
All AC timing characteristics assume an input slew rate of 1.0 V/ns. The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes. The transition time for address and command inputs is measured between VIH and VIL. For command / address input slew rate 1V/ns. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. For command / address input slew rate 0.5 V/ns and < 1.0 V/ns. This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.1
NO OPERATION (NOP)
FIGURE 6
No Operation Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
The NO OPERATION (NOP) command is used to perform a NOP to a DDR Mobile-RAM which is selected (CS = LOW). This prevents unwanted commands from being registered during idle states. Operations already in progress are not affected.
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the DDR Mobile-RAM. The DDR Mobile-RAM is effectively deselected. Operations already in progress are not affected.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.3
MODE REGISTER SET
FIGURE 7
Mode Register Set Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 Code Code = Don't Care (High)
The Mode Register and Extended Mode Register are loaded via inputs A0 - A12 (see mode register descriptions in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
FIGURE 8
Mode Register Definition
CK CK Command MRS NOP tMRD Address Code Valid = Don't Care Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - A12) Valid
TABLE 9
Timing Parameters for Mode Register Set Command
Parameter Symbol min. MODE REGISTER SET command period tMRD 2 - - 7.5 max. tCK - Unit Note
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.4
ACTIVE
FIGURE 9
ACTIVE Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 RA BA = Don't Care
BA = Bank Address RA = Row Address
Before any READ or WRITE commands can be issued to a bank within the DDR Mobile-RAM, a row in that bank must be "opened" (activated). This is accomplished via the ACTIVE command and addresses BA0, BA1, A0 - A12 (see Figure 9), which decode and select both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
(High)
FIGURE 10
Bank Activate Timings
CK CK Command A0-A12 BA0, BA1 ACT Row BA x tRRD NOP ACT Row BA y tRCD NOP NOP RD/WR Col BA y NOP
= Don't Care
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 10
Timing Parameters for ACTIVE Command
Parameter Symbol min. ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay tRC tRCD tRRD 65 22.5 15 - - - - 7.5 max. ns ns ns
1)
Unit
Note
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
2.4.5
READ
FIGURE 11
READ Command
CK CK CKE CS RAS CAS WE A0-A9 A10 BA0,BA1 CA
Enable AP
READ bursts are initiated with a READ command, as shown in Figure 11. Basic timings for the DQs are shown in Figure 12; they apply to all read operations. The starting column and bank addresses are provided with the READ command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed will start precharge at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the following illustrations, Auto Precharge is disabled.
(High)
AP
Disable AP
BA = Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 12
Basic READ Timing Parameters for DQs
CK CK tCK tCK tCH tCL
tACmax
DQS
tDQSCK tRPRE tAC tDQSQmax DO n tQH
tDQSCK
tRPST tHZ
DQ
tLZ
DO n+1 DO n+2 DO n+3 tQH tDQSCK
tACmin
DQS tRPRE
tDQSCK
tRPST tHZ
tAC DQ tLZ
tDQSQmax DO n tQH
DO n+1 DO n+2 DO n+3 tQH
DO n = Data Out from column n = Don't Care Burst Length = 4 in the case shown CAS Latency = 3 in the case shown All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC
TABLE 11
Timing Parameters for READ Command
Parameter Symbol min. DQ output access time from CK/CK DQS output access time from CK/CK DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Read preamble Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period CL = 3 CL = 2 tRPST tRAS tRC tAC tDQSCK tLZ tHZ tDQSQ tQH tQHS tRPRE 2.0 2.0 1.0 - - tHP-tQHS - 0.9 0.7 0.4 45 65 - 7.5 max. 6.5 6.5 - 6.5 0.6 - 0.75 1.1 1.1 0.6 70,000 - tCK ns ns -
6) 6)
Unit
Note
ns ns ns ns ns ns ns tCK
1)2) 1)2) 3) 3) 4) 5) 5)
-
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Parameter
Symbol min.
- 7.5 max. - -
Unit
Note
ACTIVE to READ or WRITE delay PRECHARGE command period
tRCD tRP
22.5 22.5
ns ns
6) 6)
1) The output timing reference level is VDDQ/2. 2) Parameters tAC and tQH are specified for full drive strength and a reference load of 20pF. This reference load is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested. 3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 4) tDQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 5) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round to the next higher integer.
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. The diagrams in Figure 13 show general timing for each supported CAS latency setting. DQS is driven by the DDR MobileRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
FIGURE 13
READ Burst
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n NOP NOP NOP NOP NOP
= Don't Care DO n = Data Out from column n BA, Col n = Bank A, Column n Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n pre fetch architecture). This is shown in Figure 14.
FIGURE 14
Consecutive READ Bursts
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO b DO b NOP READ BA,Col b NOP NOP NOP
= Don't Care DO n (or b) = Data Out from column n (or column b) Burst Length = 4, 8 or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7 or 15) subsequent elements of Data Out appear in the programmed order following DO b Read commands shown must be to the same device
A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive READ data is illustrated in Figure 15.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 15
Nonconsecutive READ Bursts
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO b NOP NOP READ BA,Col b NOP NOP
= Don't Care DO n (or b) = Data Out from column n (or column b) BA A Col n (b) = Bank A, Column n (b) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (b)
Full-speed random READ accesses (Burst Length = 2, 4, 8 or 16) within a page (or pages) can be performed as shown in Figure 16.
FIGURE 16
Random READ Accesses
CK CK Command Address READ BA,Col n READ BA,Col x CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO n' DO x DO x' DO b DO b' DO n' DO x DO x' DO b DO b' DO g DO g' READ BA,Col b READ BA,Col g NOP NOP
DO n, etc. = Data Out from column n, etc. n', x', etc. = Data Out elements, according to the programmed burst order BA, Col n = Bank A, Column n Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8 or 16, the burst is interrupted) Reads are to active rows in any banks
= Don't Care
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Figure 20), provided that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs. This is shown in Figure 17.
FIGURE 17
Terminating a READ Burst
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n = Don't Care NOP BST NOP NOP NOP
DO n = Data Out from column n BA, Col n = Bank A, Column n Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of Data Out appear in the programmed order following DO n
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.5.2
READ to WRITE
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 18.
FIGURE 18
READ to WRITE
CK CK Command Address READ BA,Col n CL=2 DQS DQ DM DO n Di b BST NOP WRITE BA,Col b tDQSS NOP NOP
Command Address
READ BA,Col n
BST
NOP
NOP
WRITE BA,Col b
NOP
CL=3 DQS DQ DM DO n = Data Out from column n; DI b = Data In to column b 1 subsequent element of Data Out appear in the programmed order following DO n. Data In elements are applied following DI b in the programmed order = Don't Care DO n Di b
2.4.5.3
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank (provided that Auto Precharge was not activated). The PRECHARGE command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs. This is shown in Figure 19. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Please note that part of the row precharge time is hidden during the access of the last data elements. In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same READ burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 19
READ to PRECHARGE
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n NOP PRE Bank (a or all) tRP NOP NOP ACT BA, Row
= Don't Care DO n = Data Out from column n Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 or 16 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL / 2) tCK after the READ command. Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. The ACTIVE command may be applied if tRC has been met.
2.4.6
BURST TERMINATE
FIGURE 20
BURST TERMINATE Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
The BURST TERMINATE command is used to truncate READ bursts (with Auto Precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in Figure 17.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.7
WRITE
WRITE bursts are initiated with a WRITE command, as shown in Figure 21. Basic timings for the DQs are shown in Figure 22; they apply to all write operations.The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge is disabled.
FIGURE 21
WRITE Command
CK CK CKE CS RAS CAS WE A0-A9 A10 BA0,BA1 CA
Enable AP
(High)
AP
Disable AP
BA = Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 22
Basic WRITE Timing Parameters for DQs
CK CK Case 1: tDQSS = min DQS tWPRES tWPRE tDS DQ, DM Case 2: tDQSS = max DQS tWPRES tWPRE tDS DQ, DM DI n tDH tDQSL DI n tDSS tWPST tDSS tDH tDQSL tDQSS tDQSH tDSH tDSH tWPST tCK tCH tCL
tDQSS
tDQSH
DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n. Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the 25% window of the corresponding positive clock edge.
= Don't Care
TABLE 12
Timing Parameters for WRITE Command
Parameter Symbol min. DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width DQS falling edge to CK setup time DQS falling edge hold time from CK Write preamble setup time fast slew rate slow slew rate fast slew rate slow slew rate tDIPW tDQSS tDQSH tDQSL tDSS tDSH tWPRES tDH tDS 0.75 0.85 0.75 0.85 1.7 0.75 0.4 0.4 0.2 0.2 0 - - - - - 1.25 0.6 0.6 - - - ns tCK tCK tCK tCK tCK ns ns - 7.5 max. ns
1)2)3) 1)2)4) 1)2)3) 1)2)4) 5)
Unit
Note
- - - - -
6)
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Parameter
Symbol min.
- 7.5 max. 0.6 - 70,000 - - - -
Unit
Note
Write postamble Write preamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay WRITE recovery time Internal write to Read command delay PRECHARGE command period
tWPST tWPRE tRAS tRC tRCD tWR tWTR tRP
0.4 0.25 45 65 22.5 15 1
tCK tCK ns ns ns ns tCK ns
7)
-
8) 8) 8) 8)
-
8)
22.5 - 1) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 3) Input slew rate 1.0 V/ns. 4) Input slew rate 0.5V/ns and < 1.0 V/ns. 5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test. 6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 8) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command, and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in Figure 23 show the two extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data is ignored.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 23
WRITE Burst (min. and max. tDQSS)
CK CK Command Address WRITE BA,Col b tDQSSmin DQS DQ DM tDQSSmax DQS DQ DM DI b = Data In to column b. 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. A10 is LOW with the WRITE command (Auto Precharge is disabled) Di b Di b NOP NOP NOP NOP NOP
= Don't Care
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any clock cycle following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x clock cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n pre fetch architecture). Figure 24 shows concatenated WRITE bursts of 4.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 24
WRITE to WRITE (min. and max. tDQSS)
CK CK Command Address WRITE BA,Col b tDQSSmin DQS DQ DM tDQSSmax DQS DQ DM DI b (n) = Data In to column b (column n) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. Non-interrupted bursts of 4 are shown. Each WRITE command may be to any active bank Di b Di n Di b Di n NOP WRITE BA,Col n NOP NOP NOP
= Don't Care
An example of non-consecutive WRITEs is shown in Figure 25.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 25
Non-Consecutive WRITE to WRITE (max. tDQSS)
CK CK Command Address DQS DQ DM DI b (n) = Data In to column b (or column n). 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. Non-interrupted bursts of 4 are shown. Each WRITE command may be to any active bank and may be to the same or different devices. Di b Di n WRITE BA,Col b tDQSSmax NOP NOP WRITE BA,Col n NOP NOP
= Don't Care
Full-speed random WRITE accesses within a page or pages can be performed as shown in Figure 26.
FIGURE 26
Random WRITE Cycles (max. tDQSS)
CK CK Command Address DQS DQ DM DI b etc. = Data In to column b, etc. . = Don't Care b', etc. = the next Data In following DI b, etc. according to the programmed burst order Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4, 8 or 16, burst would be truncated. Each WRITE command may be to any active bank and may be to the same or different devices. Di b Di b' Di x Di x' Di n Di n' Di a Di a' WRITE BA,Col b WRITE BA,Col x tDQSSmax WRITE BA,Col n WRITE BA,Col a WRITE BA,Col g NOP
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.7.1
WRITE to READ
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR (WRITE to READ) should be met as shown in Figure 27.
FIGURE 27
Non-Interrupting WRITE to READ (max. tDQSS)
CK CK Command Address DQS DQ DM DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. t W TR is referenced from the positive clock edge after the last Data In pair. A10 is LOW with the W RITE command (Auto Precharge is disabled) The READ and W RITE commands are to the same device but not necessarily to the same bank. Di b WRITE BA,Col b tDQSSm ax tW TR NOP NOP NOP READ BA,Col n CL=3 NOP NOP
= Don't Care
Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 28. Note that only the datain pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in Figure 28.
FIGURE 28
Interrupting WRITE to READ (max. tDQSS)
CK CK Com m and Address DQS DQ DM D I b = D ata In to colum n b. D O n = D ata O ut from colum n n. An interrupted burst of 4 is show n, 2 data elem ents are w ritten. 3 subsequent elem ents of D ata In are applied in the program m ed order follow ing D I b. t W TR is referenced from the positive clock edge after the last D ata In pair. A10 is LO W w ith the W RITE com m and (Auto Precharge is disabled) The R EAD and W R ITE com m ands are to the sam e device but not necessarily to the sam e bank. Di b DO n WRITE BA,Col b t DQSSm ax t W TR NOP NOP R EAD BA,Col n C L=3 NOP NO P NO P
= Don't C are
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.7.2
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 29.
FIGURE 29
Non-Interrupting WRITE to PRECHARGE (max. tDQSS)
CK CK Command Address DQS DQ DM DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. tWR is referenced from the positive clock edge after the last Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) Di b WRITE BA,Col b tDQSSmax tWR NOP NOP NOP NOP PRE BA a (or all)
= Don't Care
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 30. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a WRITE burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 30
Interrupting WRITE to PRECHARGE (max. tDQSS)
CK CK Command Address DQS DQ DM Di b *1 *1 *1 *1 = Don't Care WRITE BA,Col b tDQSSmax tWR *2 NOP NOP NOP PRE BA a (or all) NOP
DI b = Data In to column b . An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. tWR is referenced from the positive clock edge after the last desired Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) *1 = can be Don't Care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes Don't Care at this point
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.8
PRECHARGE
FIGURE 31
PRECHARGE Command
CK CK CKE CS RAS CAS WE A0-A9 A11,A12
All Banks
The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open rows in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
(High)
A10
One Bank
BA0,BA1
BA = Don't Care
BA = Bank Address (if A10 = L, otherwise Don't Care)
TABLE 13
Timing Parameters for PRECHARGE Command
Parameter Symbol min. ACTIVE to PRECHARGE command period PRECHARGE command period WRITE recovery time tRAS tRP tWR 45 22.5 15 - - - 7.5 max. 70,000 ns ns ns
1) 1) 1)
Unit
Note
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round to the next higher integer.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type.
2.4.9
AUTO REFRESH and SELF REFRESH
The DDR Mobile-RAM requires a refresh of all rows in an rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. Dividing the number of rows into the rolling 64ms interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing.
2.4.9.1
AUTO REFRESH
FIGURE 32
AUTO REFRESH Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
Auto Refresh is used during normal operation of the DDR Mobile-RAM. The command is non persistent, so it must be issued each time a refresh is required. A minimum time tRFC is required between two AUTO REFRESH commands. The same rule applies to any access command after the Auto Refresh operation. All banks must be precharged prior to the AUTO REFRESH command.The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The DDR Mobile-RAM requires Auto Refresh cycles at an average periodic interval of tREFI (max.).Partial array mode has no influence on Auto Refresh mode. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to the DDR Mobile-RAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 33
Auto Refresh
CK CK Command Address A10 (AP) DQ Pre All
High-Z
tRP PRE NOP ARF
tRFC NOP NOP ARF
tRFC NOP NOP ACT Ba A, Row n Row n
Ba A, Row n = Bank A, Row n
= Don't Care
2.4.9.2
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR Mobile-RAM, even if the rest of the system is powered down. When in the Self Refresh mode, the DDR Mobile-RAM retains data without external clocking. The DDR Mobile-RAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are "Don't Care" during Self Refresh. The user may halt the external clock one clock after Self Refresh entry is registered.
FIGURE 34
SELF REFRESH Entry Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The device executes a minimum of one AUTO REFRESH command internally once it enters Self Refresh mode. The clock is internally disabled during Self Refresh operation to save power. The minimum time that the device must remain in Self Refresh mode is tRFC. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in progress.The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is recommended.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 35
Self Refresh Entry and Exit
CK CK tRP CKE Command Address A10 (AP) DQ Pre All
High-Z
> tRFC
tXSR
tRFC
PRE
NOP
ARF
NOP
NOP
NOP
ARF
NOP
ACT Ba A, Row n Row n
Enter Self Refresh Mode
Exit from Self Refresh Mode
Any Command (Auto Refresh Recommended)
= Don't Care
TABLE 14
Timing Parameters for AUTO REFRESH and SELF REFRESH Commands
Parameter Symbol min. AUTO REFRESH to ACTIVE/AUTO REFRESH command period PRECHARGE command period Self refresh exit to next valid command delay Refresh period Average periodic refresh interval (8192 rows) tRFC tRP tXSR tREF tREFI 75 22.5 120 - - - - - 64 7.8 - 7.5 max. ns ns ns ms s
1) 1) 1)
Unit
Note
-
2)
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round to the next higher integer. 2) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.4.10
POWER-DOWN
FIGURE 36
Power-Down Entry Command
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. In power-down mode, CKE LOW must be maintained, and all other input signals are "Don't Care". The minimum power-down duration is specified by tCKE. However, power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid command may be applied tXP after exit from power-down.
FIGURE 37
Power-Down Entry and Exit
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 15
Timing Parameters for POWER-DOWN
Parameter Symbol min. Exit power down delay CKE minimum low time tXP tCKE tCK + tIS 2 - - - 7.5 max. ns tCK - Unit Note
2.4.10.1
DEEP POWER-DOWN
Deep Power-Down mode is a unique feature of DDR Mobile-RAMs for extremely low power consumption. Deep Power-Down mode is entered using the BURST TERMINATE command (cf Table 6) except that CKE is LOW. All internal voltage generators are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged. The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence as for power-up initialization, including the 200s initial pause, has to be applied before any other command may be issued (cf. Figure 4).
2.4.11
CLOCK STOP
Stopping the clock during idle periods is a very effective method to reduce power consumption. The DDR Mobile-RAM supports clock stop in case: * the last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pulses per access command depends on the device's AC timing parameters and the clock frequency (see Table 16); * the related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met; * CKE is held HIGH. When all conditions have been met, the device is either in "idle" or "row active" state (cf. Figure 4), and clock stop mode may be entered with CK held LOW and CK held HIGH. Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics. Figure 38 illustrates the clock stop mode: * initially the device is in clock stop mode; * the clock is restarted with the rising edge of T0 and a NOP on the command inputs; * with T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command has completed; * Tn is the last clock pulse required by the access command latched with T1 * the timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required by this command and the clock is then stopped.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
FIGURE 38
Clock Stop
CK CK CKE Timing Condition Command
NOP CMD NOP NOP NOP
T0
T1
T2
Tn
Clock Stopped
Exit Clock Stop
Valid Command
Enter Clock Stop
= Don't Care
TABLE 16
Minimum Number of Required Clock Pulses per Access Command
Command ACTIVE READ (Auto-Precharge Disabled) READ (Auto-Precharge Enabled) WRITE (Auto-Precharge Disabled) WRITE (Auto-Precharge Enabled) PRECHARGE AUTO REFRESH MODE REGISTER SET Timing Condition tRCD (BL / 2) + CL [(BL / 2) + tRP]; [(BL / 2) + CL] 1 + (BL / 2) + tWR 1 + (BL / 2) + tDAL tRP tRFC tMRD 3 5 5 5 8 3 10 2 - 7.5 Unit tCK tCK tCK tCK tCK tCK tCK tCK
1) 1)2) 1)2)3) 1)2) 1)2) 1) 1)
Note
1) These parameters depend on the operating frequency; the number of clock cycles shown are calculated for a clock frequency of 133 MHz for -7.5. 2) The values apply for a burst length of 4 and a CAS latency of 3. 3) Both timing conditions need to be satisfied; if not equal, the larger value applies
2.4.12
Clock Frequency Change
Depending on system considerations, it might be desired to change the DDR Mobile-RAM's clock frequency while the device is powered up. The DDR Mobile-RAM supports a clock frequency change when the device is in: * self refresh mode (see Figure 35); * power-down mode (see Figure 37); * clock stop mode (see Figure 38). Once the clock runs stable at the new clock frequency, the timing conditions for exiting these states have to be met before applying the next access command. It should be pointed out that a continuous frequency drift is not considered a stable clock and therefore is not supported.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
2.5
Function Truth Tables
TABLE 17
Truth Table - CKE
CKEn-1 L L CKEn Current State Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H
1) 2) 3) 4) 5) 6)
Command X X X DESELECT or NOP DESELECT or NOP X DESELECT or NOP DESELECT or NOP AUTO REFRESH BURST TERMINATE
Action Maintain Power-Down Maintain Self Refresh Maintain Deep Power-Down Exit Power-Down Exit Self Refresh Exit Deep Power-Down Enter Precharge Power-Down Enter Active Power-Down Enter Self Refresh Enter Deep Power-Down
Note
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4)6) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)
H
see Table 18 and Table 19
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tXP or tXSR period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
TABLE 18
Current State Bank n - Command to Bank n
Current State Any Idle CS H L L L L Row Active L L L Read (AutoPrecharge Disabled) L L L L RAS X H L L L H H L H H L H CAS X H H L L L L H L L H H WE X H H H L H L L H L L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) READ (truncate Read and start new Read burst) WRITE (truncate Read and start new Write burst) PRECHARGE (truncate Read and start Precharge) BURST TERMINATE Note
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6)8) 1)2)3)4)5)6)8) 1)2)3)4)5)6)9) 1)2)3)4)5)6)8) 1)2)3)4)5)6)8)10) 1)2)3)4)5)6)9) 1)2)3)4)5)6)11)
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Current State Write (AutoPrecharge Disabled)
CS L L L
RAS H H L
CAS L L H
WE H L L
Command / Action READ (truncate Write and start Read burst) WRITE (truncate Write and start Write burst)
Note
1)2)3)4)5)6)8)12) 1)2)3)4)5)6)8)
power-down or self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 19. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read with AP Enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR Mobile-RAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR Mobile-RAM is in the "all banks idle" state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 12) Requires appropriate DM masking.
1)2)3)4)5)6)9)12) PRECHARGE (truncate Write burst, start Precharge) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the previous state was
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 19
Current State Bank n - Command to Bank m (different bank)
Current State Any Idle Row Activating, Active, or Precharging CS H L X L L L L Read (AutoPrecharge Disabled) L L L L Write (AutoPrecharge Disabled) L L L L Read (with Auto- L Precharge) L L L Write (with Auto- L Precharge) L L L RAS X H X L H H L L H H L L H H L L H H L L H H L CAS X H X H L L H H L L H H L L H H L L H H L L H WE X H X H H L L H H L L H H L L H H L L H H L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) Note
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)8) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7)9) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)8) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)
power-down or self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Read with AP Enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state).
1)2)3)4)5)6) PRECHARGE (Deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the previous state was
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
4) 5) 6) 7) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. All states and sequences not shown are illegal or reserved. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 9) Requires appropriate DM masking.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 20
Absolute Maximum Ratings
Parameter Symbol min. Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operating Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Commercial Extended Values max. 2.7 2.7 V V V V C C C W mA Unit
VDD VDDQ VIN VOUT TC TC TSTG PD IOUT
-0.3 -0.3 -0.3 -0.3 0 -25 -55 - -
VDDQ + 0.3 VDDQ + 0.3
+70 +85 +150 0.7 50
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 21
Pin Capacitances
Parameter Symbol min. Input capacitance: CK, CK Delta input capacitance: CK, CK Input capacitance: all other input-only balls Delta input capacitance: all other input-only balls Input/output capacitance: DQ, DQS, DM Delta input/output capacitance: DQ, DQS, DM Values max. 6.5 0.5 6.5 1.0 6.0 1.0 pF pF pF pF pF pF
1)2)3)
Unit
Note
CI1 CDI1 CI2 CDI2 CIO CDIO
4.0 - 4.0 - 3.0 -
1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other balls (except the ball under test) are floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level. 3) Although DM is an input-only ball, it's input capacitance models the input capacitance of the DQ and DQS balls.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
TABLE 22
Electrical Characteristics
Parameter Symbol min. Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Input high voltage Input low voltage Clock Inputs (CK, CK) DC input voltage DC input differential voltage AC input differential voltage AC differential cross point voltage Data Inputs (DQ, DM, DQS) DC input high voltage DC input low voltage AC input high voltage AC input low voltage Data Outputs (DQ, DQS) Output high voltage (IOH = -0.1 mA) Output low voltage (IOL = 0.1 mA)
1) 2) 3) 4)
Values max. 1.90 1.90 1.0 1.5
Unit
Note
VDD VDDQ IIL IOL VIH VIL VIN VID(DC) VID(AC) VIX VIHD(DC) VILD(DC) VIHD(AC) VILD(AC) VOH VOL
1.70 1.70 -1.0 -1.5 0.8 x VDDQ -0.3 -0.3 0.4 x VDDQ 0.6 x VDDQ 0.4 x VDDQ 0.7 x VDDQ -0.3 0.8 x VDDQ -0.3 0.9 x VDDQ -
V V A V V V V V V V V V V V V
1)2) 1)2) 1) 1)
Address and Command Inputs (BA, BA1, CKE, CS, RAS, CAS, WE)
VDDQ + 0.3 0.2 x VDDQ
VDDQ + 0.3
1) 1)
1) 1)3) 1)3) 1)4)
VDDQ + 0.6 VDDQ + 0.6 0.6 x VDDQ VDDQ + 0.3
0.3 x VDDQ
1) 1) 1) 1)
VDDQ + 0.3 0.2 x VDDQ
- 0.1 x VDDQ
1) 1)
See Table 25 and Figure 40 for overshoot and undershoot definition.
VDDmax = VDDQmax = 1.95V permitted for Clock Frequency (fCKmax) 133MHz (CL = 3) and commercial temperature range -0 C TJ 70 C.
VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to be equal to 0.5 x VDDQ and must track variations in the DC level.
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
3.2
AC Characteristics
TABLE 23
AC Characteristics
Parameter Symbol min. DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Address and control input setup time Address and control input hold time Address and control input pulse width DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width DQS falling edge to CK setup time DQS falling edge hold time from CK MODE REGISTER SET command period Write preamble setup time Write postamble Write preamble Read preamble Read postamble CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate - 7.5 max. 6.5 6.5 0.55 0.55 - - - - - - - - - - - - - 6.5 0.6 - 0.75 1.25 0.6 0.6 - - - - 0.6 - 1.1 1.1 0.6 ns ns ns ns ns ns ns ns ns ns ns
1)2)3)9)10)11) 1)2)3)9)10)12) 1)2)3)9)10)11) 1)2)3)9)10)12) 1)2)3)13) 1)2)3)6)14)15) 1)2)3)12)15) 1)2)3)11)14)15) 1)2)3)12)14)15) 1)2)3)13) 1)2)3)16) 1)2)3)16) 1)2)3)17) 1)2)3)7) 1)2)3)7) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3) 1)2)3)18) 1)2)3)19) 1)2)3) 1)2)3)20)
Unit
Note
tAC tDQSCK tCH tCL tHP tCK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST tWPRE tRPRE tRPST
2.0 2.0 0.45 0.45 7.5 15 0.75 0.85 0.75 0.85 1.7 1.3 1.5 1.3 1.5 3.0 1.0 - - tHP-tQHS - 0.75 0.4 0.4 0.2 0.2 2 0 0.4 0.25 0.9 0.7 0.4
ns ns
1)2)3)4)5) 1)2)3)4)5) 1)2)3) 1)2)3) 1)2)3)6)7) 1)2)3)8)
tCK tCK
ns ns
min (tCL,tCH)
tCK tCK tCK tCK tCK tCK
ns
tCK tCK tCK tCK tCK
1)2)3)
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Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Parameter
Symbol min.
- 7.5 max. 70,000 - - - - - - - - - - 64 7.8
Unit
Note
tRAS ACTIVE to ACTIVE command period tRC AUTO REFRESH to ACTIVE/AUTO REFRESH command period tRFC ACTIVE to READ or WRITE delay tRCD PRECHARGE command period tRP ACTIVE bank A to ACTIVE bank B delay tRRD WRITE recovery time tWR Auto precharge write recovery + precharge time tDAL Internal write to Read command delay tWTR Self refresh exit to next valid command delay tXSR Exit power down delay tXP CKE minimum high or low time tCKE Refresh period tREF Average periodic refresh interval (8192 rows) tREFI
ACTIVE to PRECHARGE command period
45 65 75 22.5 22.5 15 15 1 120
ns ns ns ns ns ns ns
1)2)3)21) 1)2)3)21) 1)2)3)21) 1)2)3)21) 1)2)3)21) 1)2)3)21) 1)2)3)21) 1)2)3)22) 1)2)3) 1)2)3)21) 1)2)3) 1)2)3) 1)2)3) 1)2)3)23)
tCK tCK
ns ns
tCK+ tIS
2 - -
tCK
ms s
1) All parameters assume proper device initialization. 2) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VDDQ/2. 3) All AC timing characteristics assume an input slew rate of 1.0 V/ns. 4) The output timing reference level is VDDQ/2. 5) Parameters tAC and tDQSCK are specified for full drive strength and a reference load (see Figure 39). This circuit is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tDQSCK are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested. 6) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 7) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 8) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes. 9) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 11) Input slew rate 1.0 V/ns. 12) Input slew rate 0.5V/ns and < 1.0 V/ns. 13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test. 14) The transition time for address and command inputs is measured between VIH and VIL. 15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. 16) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 17) tDQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 19) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
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20) A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 21) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round to the next higher integer. 22) tDAL = (tWR / tCK) + (tRP / tCK): for each of the terms above, if not already an integer, round to the next higher integer. 23) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
FIGURE 39
Measurement with Reference Load
TABLE 24
Output Slew Rate Characteristics
Parameter Pull-up and Pull-down Slew Rate (Full Drive Buffer) Pull-up and Pull-down Slew Rate (Half Drive Buffer) Output Slew Rate Matching Ratio (Pull-up to Pull-down) Typical Range TBD TBD 0.7 0.3 0.7 Minimum 2.5 1.0 1.4 Maximum Unit V/ns V/ns Note
1)2)
1)2)
1)3)
1) Output slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 2) The parameter is measured using a 20pF capacitive load connected to VSSQ. 3) The ratio of the pull-up slew rate to the pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.
TABLE 25
AC Overshoot / Undershoot Specification
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD Maximum undershoot area below VSS 0.9 0.9 3.0 3.0 Maximum Unit V V V-ns V-ns Note - - - -
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FIGURE 40
AC Overshoot and Undershoot Definition
3.0 Overshoot 2.5 2.0 1.5 Voltage (V) 1.0 0.5 0 -0.5 -1.0 -1.5 0 1 2 3 time (ns) 4 5 6 7 Undershoot VSS Max. Amplitude = 0.9V Max. Area = 3V-ns
VDD
3.3
Operating Currents
TABLE 26
Maximum Operating Currents
Parameter & Test Conditions Symbol Values - 7.5 Operating one bank active-precharge current: address inputs are SWITCHING; data bus inputs are STABLE Unit Note1)2)3)
4)
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid commands;
IDD0
100
mA
IDD2P Precharge power-down standby current: all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stop: all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
1.40
mA
IDD2PS
1.20
mA
Precharge non power-down standby current: IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE Precharge non power-down standby current with clock stop: all banks idle, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
30
mA
IDD2NS
3.0
mA
Active power-down standby current: IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
4
mA
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Parameter & Test Conditions
Symbol
Values - 7.5
Unit
Note1)2)3)
4)
Active power-down standby current with clock stop: IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active non power-down standby current: one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
3.0
mA
IDD3N
44
mA
Active non power-down standby current with clock stop: IDD3NS one bank active, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Operating burst read current: one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA; address input are SWITCHING; 50% data change each burst transfer Operating burst write current: one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer Auto-Refresh current:
5.0
mA
IDD4R
150
mA
IDD4W
150
mA
tRC = tRFCmin; tCK = tCKmin; burst refresh; CKE is HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE Self refresh current: CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus inputs are STABLE Deep Power Down current
IDD5
270
mA
IDD6
see Table 27 505)
A
IDD8
A
1) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade. 2) Input slew rate is 1.0 V/ns. 3) Definitions for IDD: LOW is defined as VIN 0.1 * VDDQ; HIGH is defined as VIN 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE 4) All parameters are measured with no output loads. 5) IDD8 value shown as typical
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TABLE 27
Self Refresh Currents
Parameter & Test Conditions Max. Symbol Temperature Values HYE18M1G320BF Typ. Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter array activation (PASR = 010) 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C Max. 1800 -- -- -- 1560 -- -- -- 1340 -- -- -- -- 1020 640 560 -- 740 480 420 -- 580 420 340 1560 -- -- -- 1340 -- -- HYB18M1G320BF Typ. -- 1800 -- -- Max. A
1)
Units
Note
IDD6
1520 1020 640 560 1080 740 480 420 840 580 420 340
1) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component's actual temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85C. Typ. values are obtained from device characterization.
3.4
Pull-up and Pull-down Characteristics
Figure 41 shows the characteristics of full and half drive strength. It is specified under best and worst process variation /condition. Temperature (Tcase): Minimum = 0 C / -25C, Maximum = 70C.
FIGURE 41
Full Drive Strength and Half Drive Strength
Full Drive Strength IV Curves 75.0 50.0 25.0 0.0 -25.0 -50.0 -75.0 0.0 0.5 1.0 1.5
PD Min PD Max PU Min PU Max
Half Drive Strength IV Curves 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 0.0 0.5 1.0 1.5
PD Min PD Max PU Min PU Max
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4
Package Outline
FIGURE 42
90-ball PG-VFBGA-90-5
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List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing Parameters for ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Timing Parameters for READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing Parameters for WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timing Parameters for PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Timing Parameters for AUTO REFRESH and SELF REFRESH Commands. . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timing Parameters for POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Minimum Number of Required Clock Pulses per Access Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output Slew Rate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC Overshoot / Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Maximum Operating Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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List of Illustrations
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Standard ballout 1-Gbit DDR Mobile-RAM (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address / Command Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 WRITE Burst (min. and max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WRITE to WRITE (min. and max. tDQSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Non-Consecutive WRITE to WRITE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Random WRITE Cycles (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Non-Interrupting WRITE to READ (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupting WRITE to READ (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Non-Interrupting WRITE to PRECHARGE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupting WRITE to PRECHARGE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power-Down Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clock Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Measurement with Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC Overshoot and Undershoot Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Full Drive Strength and Half Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 90-ball PG-VFBGA-90-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Rev.1.00, 2007-03 02022006-J7N7-GYFP
60
Data Sheet
HY[B/E]18M1G320BF 1-Gbit DDR Mobile-RAM
Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.6 2.4.7 2.4.7.1 2.4.7.2 2.4.8 2.4.8.1 2.4.9 2.4.9.1 2.4.9.2 2.4.10 2.4.10.1 2.4.11 2.4.12 2.5 3 3.1 3.2 3.3 3.4 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . 14 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DEEP POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CLOCK STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-up and Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 52 55 57
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Rev.1.00, 2007-03 02022006-J7N7-GYFP
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Data Sheet
Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

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